VIP Lane

Overview

VIP Lane® is an innovative software solution for fact-based design quality monitoring. Working within customers' design flows, VIP Lane turns customers' design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams.

VIP Lane® addresses the challenges of Design-for-Reuse and Design Quality Closure from three complementary perspectives:

a. Design methodology perspective, or "How can we maintain and deploy best design practices throughout a semiconductor company while maximizing adoption by design teams?"

	b. Designers' perspective, or "Can I check that my work is compliant with corporate quality rules while avoiding additional time or overhead?"

c. Project managers' perspective, or "How can we monitor progress and get to IP quality closure on schedule despite all design dynamics?"

VIP Lane® answers these questions by implementing a 3-step strategy:

	1. Import your Design Quality Checks by using one of the available libraries or by creating your own library in a few hours
	2. Configure and Automate Dashboards by editing software sensors that link the Quality Checks to your current design and verification flow
	3. Monitor Design Quality Closure by deploying the dashboards and issuing quality reports on the fly

Once deployed, VIP Lane® is a web server application that is integrated with and complements the electronic design automation (EDA) and product lifecycle management tools that typically constitute semiconductor design flows.

VIP Lane® tracks and captures all parameters and objects affecting design quality, from multiple sources throughout the IP or SoC design and integration lifecycle. Then, taking advantage of its patented design quality abstraction layer, it offers:

Non intrusive assistance to IP designers
This capability is available in the form of checklists that reflect the set of quality items that designers need to keep an eye on. The checklists complete themselves automatically, on the basis of the latest information found in the customer flow, and address the most critical areas of design quality and design reuse: specifications, architecture, front-end design, back-end design, verification, IP packaging, software development and overall project management.
Fact-based quality closure monitoring to project managers
This capability takes the form of dashboards generated on the fly from the customer flow outputs. The dashboards are available in different forms (single IP, multi IP...) and are always up-to-date, by construction. They complement nicely the other mechanisms that projects managers have for tracking resources and schedules, and make a major contribution to timely and accurate quality closure.